Current trends in the semiconductor and electronics industry require memory devices to be made smaller, faster and require less power consumption. One reason for these trends is that more personal devices are being manufactured that are relatively small and portable, thereby relying on battery power. In addition to being smaller and more portable, personal devices are also requiring increased memory and more computational power and speed. In light of all these trends, there is an ever increasing demand in the industry for smaller, faster, and lower power dissipation memory cells and transistors used to provide the core functionality of these memory devices. Such memory devices are used for storage of data, program code, calibration, trimming and/or unit identification information in personal computer systems, embedded processor-based systems, credit and ID cards, video and communications devices and the like. Preferably, devices that include a memory will be configured such that if power is lost, the memory data will be retained. Such a memory device that retains data without power is called a non-volatile memory (NVM).
Semiconductor memories can, for example, be characterized as volatile random access memories (RAMs) or nonvolatile read only memories (ROMs), where RAMs can either be static (SRAM) or dynamic (DRAM) differing mainly in the manner by which they store a state of a bit. Examples of conventional NVM memory include electrically erasable, programmable read only memory (EEPROM), and Flash EEPROM or “commodity Flash” memory.
NVM memories range from very large arrays, such as commodity and embedded EEPROM arrays, and Flash EEPROM arrays (e.g., implementing thousands to many millions of bits), where the need for a smaller area may justify considerably greater process complexity, through the very small examples (e.g., implementing as few as single digits to thousands of bits) where keeping the added process complexity to a minimum justifies a larger area for each bit. Thus, the very large arrays generally utilize greater process complexity to obtain smaller cells, while smaller array applications may utilize less process complexity to save process costs while utilizing larger area cells.
For example, It is common to add as many a six photo mask operations and associated processing steps in an effort to achieve a high density of memory bits when embedding Flash memory to digital CMOS. Some of these process operations that are used to fabricate higher density EEPROM (e.g., stack etch, where multiple layers are etched or patterned using a single masking layer, or additional layers of poly-crystalline silicon and multiple thicknesses of gate or tunnel oxide) are operations that are not normally required to build designs without EEPROM. Thus, these process operations add cost and may require specialized equipment and skills.
Accordingly, single layer poly-silicon (SLP) EEPROM arrays may address the need for device applications at the lower end of the spectrum of process costs. SLP EEPROMs may be built with simpler silicon processes relative to the higher density Flash and EEPROM classes built with more complex silicon processes. For example, when a digital CMOS device is needed, an embedded SLP EEPROM memory may often be added with little or no added wafer cost to the CMOS device. However, process complexity and circuit techniques, not the number of poly layers, are the real differentiating properties between SLP EEPROM, for example, and Flash EEPROM.
In many SLP EEPROM implementations that minimize process complexity, several circuits may be replicated for each bit or memory location (e.g., level-shifters and sense amplifier or read latches). It is also common in these implementations to use four or more high voltage transistors per bit, which increases the area per bit to levels unacceptable for anything other than a NVM memory with a small number of bits.
The basic EEPROM storage element is called a floating gate transistor. One prior-art floating-gate transistor has a source S, a polysilicon floating gate FG storage node with no connection permitted, and a drain D. The gate is said to float without any direct electrical contact, embedded within a high-quality insulator. A charge placed on such a floating gate typically represents a data state or bit of data, and may be retained for a decade or more.
EEPROM memories using Fowler-Nordheim (F-N) tunneling are often programmed by applying a relatively high voltage level of from about 5 volts to about 30 volts across a tunneling region (e.g., a tunnel oxide or gate oxide) for a controlled period of time. Typical tunnel oxide thicknesses range from about 50 Angstroms to about 200 Angstroms. The silicon under at least part of the tunnel oxide area is doped sufficiently to avoid excessive depletion when programming voltages are applied. Electrons are placed on the floating gate storage node as charge flows through the gate oxide or tunnel oxide, reducing the electric field as the current falls towards zero. A reversed polarity results in reverse charge flow, providing the ability for a large but finite number of write/erase cycles.
EEPROM memory is typically arranged as a matrix of memory cells fabricated in an integrated circuit chip, and address decoding in the chip allows access to each cell for read/write functions. These Flash memory cells are often arranged in rows so that blocks of data such as words or bytes can be written or read simultaneously. Flash EPROM and EEPROM memory cells have many variations.
In a conventional memory array configuration, only a subset of the cells is typically addressed at one time. During write operations of several prior art memory arrays, for example, bias conditions must be such that the unaddressed cells in the accessed row or column are not subject to upset. Therefore, care is often taken during write operations to avoid reducing the stability of the data stored in unaddressed cells.
Accordingly, there is a need for an improved SLP EEPROM array structure and method of operating the EEPROM array in a manner that provides high density array structures with little or no added wafer cost, and/or without using high voltage transistors, while avoiding data upsets to the unselected memory cells during program and erase operations in NVM memory devices.